ENTITY dp_rom4_buf IS
PORT (
  i0	: in  BIT;
  i1	: in  BIT;
  i0x	: out BIT;
  i1x	: out BIT;
  ni0x	: out BIT;
  ni1x	: out BIT;
  vdd	: in  BIT;
  vss	: in  BIT
);
END dp_rom4_buf;

ARCHITECTURE vbe OF dp_rom4_buf IS

BEGIN
  ASSERT (vdd and not vss)
  REPORT "power supply is missing on dp_rom4_buf"
  SEVERITY WARNING;

  i0x <= i0;
  i1x <= i1;
  ni0x <= not i0;
  ni1x <= not i1;

END;