-- VHDL data flow description generated from `pot_sp`
--		date : Thu Feb 23 17:09:25 1995


-- Entity Declaration

ENTITY pot_sp IS
  GENERIC (
    CONSTANT area : NATURAL := 86000;	-- area
    CONSTANT rup : NATURAL := 684404;	-- rup
    CONSTANT rdown : NATURAL := 24	-- rdown
  );
  PORT (
  i : in BIT;	-- i
  b : in BIT;	-- b
  pad : out MUX_BIT BUS;	-- pad
  ck : in BIT;	-- ck
  vdde : in BIT;	-- vdde
  vddi : in BIT;	-- vddi
  vsse : in BIT;	-- vsse
  vssi : in BIT	-- vssi
  );
END pot_sp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF pot_sp IS
  SIGNAL b1 : BIT;		-- b1
  SIGNAL b2 : BIT;		-- b2
  SIGNAL b3 : BIT;		-- b3
  SIGNAL b4 : BIT;		-- b4
  SIGNAL b5 : BIT;		-- b5
  SIGNAL b6 : BIT;		-- b6

BEGIN
  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
    REPORT "power supply is missing on pot_sp"
    SEVERITY WARNING;

  b6 <= b5;
  b5 <= b4;
  b4 <= b3;
  b3 <= b2;
  b2 <= b1;
  b1 <= b;
	label0 : BLOCK (b6 = '1')
	BEGIN
	pad <= GUARDED i;
	END BLOCK label0;
END;