entity RAM_SENSE_DATA is

  port
    (
    bit0     : inout wor_bit bus;
    Nbit0    : inout wor_bit bus;
    bit1     : inout wor_bit bus;
    Nbit1    : inout wor_bit bus;
    AD0X     : in    bit        ;
    NAD0X    : in    bit        ;
    SENSEX   : in    bit        ;
    NSENSEX  : in    bit        ;
    PRECHX   : in    bit        ;
    WRITEX   : in    bit        ;
    DIN      : in    bit        ;
    DOUT     : out   mux_bit bus;
    VDD      : in    bit        ;
    VSS      : in    bit
    );

end RAM_SENSE_DATA;

architecture vbe of RAM_SENSE_DATA is

begin

  assert (VDD = '1' and VSS = '0')
    report "power supply is missing on ram_sense_data"
    severity WARNING;

  assert ((AD0X   xor NAD0X  ) = '1')
    report "conflicting ad0x / nad0x in ram_sense_data"
    severity WARNING;

  assert ((SENSEX xor NSENSEX) = '1')
    report "conflicting sensex / nsensex in ram_sense_data"
    severity WARNING;

  WRITE_0 : block (NAD0X = '1' and WRITEX = '1')
  begin
    BIT0  <= guarded     DIN;
    NBIT0 <= guarded not DIN;
  end block;

  WRITE_1 : block (AD0X  = '1' and WRITEX = '1')
  begin
    BIT1  <= guarded     DIN;
    NBIT1 <= guarded not DIN;
  end block;

  SENSE_0 : block (PRECHX = '0' and WRITEX = '0' and (BIT0 xor NBIT0) = '1')
  begin
    BIT0  <= guarded BIT0 ;
    NBIT0 <= guarded NBIT0;
  end block;

  SENSE_1 : block (PRECHX = '0' and WRITEX = '0' and (BIT1 xor NBIT1) = '1')
  begin
    BIT1  <= guarded BIT1 ;
    NBIT1 <= guarded NBIT1;
  end block;

  DATA_OUT : block (SENSEX = '1')
  begin
    with AD0X select
      DOUT <= guarded bit0 when '0',
                      bit1 when '1';
  end block;

end;