ENTITY rom_dec_col3 IS
PORT (
  i0      : in  BIT;
  i1      : in  BIT;
  i2      : in  BIT;
  q       : out BIT;
  vdd	  : in  BIT;
  vss	  : in  BIT
);
END rom_dec_col3;

ARCHITECTURE VBE OF rom_dec_col3 IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rom_dec_col3"
  SEVERITY WARNING;

  q <= i0 and i1 and i2;
END;