--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY buf_x2 IS
PORT(
  i	: IN STD_LOGIC;
  q	: OUT STD_LOGIC
);
END buf_x2;

ARCHITECTURE RTL OF buf_x2 IS
BEGIN
  q <= i;
END RTL;