--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY halfadder_x4 IS
PORT(
  a	: IN STD_LOGIC;
  b	: IN STD_LOGIC;
  cout	: OUT STD_LOGIC;
  sout	: OUT STD_LOGIC
);
END halfadder_x4;

ARCHITECTURE RTL OF halfadder_x4 IS
BEGIN
  cout <= (a AND b);
  sout <= (a XOR b);
END RTL;