--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY mx2_x2 IS
PORT(
  cmd	: IN STD_LOGIC;
  i0	: IN STD_LOGIC;
  i1	: IN STD_LOGIC;
  q	: OUT STD_LOGIC
);
END mx2_x2;

ARCHITECTURE RTL OF mx2_x2 IS
BEGIN
  q <= ((i1 AND cmd) OR (NOT(cmd) AND i0));
END RTL;