; configuration file for scmos with lamba = 1.0 (2um process)
; 

capm2a  .00000  ; 2nd metal capacitance -- area, pf/sq-micron
capm2p  .00020  ; 2nd metal capacitance -- perimeter, pf/micron
capma   .00003  ; 1st metal capacitance -- area, pf/sq-micron
capmp   .00020  ; 1st metal capacitance -- perimeter, pf/micron
cappa   .00007  ; poly capacitance -- area, pf/sq-micron
cappp   .00020  ; poly capacitance -- perimeter, pf/micron
capda	.00030	; n-diffusion capacitance -- area, pf/sq-micron
capdp	.00030	; n-diffusion capacitance -- perimeter, pf/micron
cappda	.00030	; p-diffusion capacitance -- area, pf/sq-micron
cappdp	.00030	; p-diffusion capacitance -- perimeter, pf/micron

capga	.000816	; gate capacitance        -- area, pf/sq-micron

lambda	1.0	; microns/lambda

lowthresh  0.4	; logic low threshold as a normalized voltage

highthresh 0.6	; logic high threshold as a normalized voltage

cntpullup 0	; irrelevant, cmos technology; no depletion transistors

diffperim 0	; don't include diffusion perimeters for sidewall cap.

subparea 0	; poly over transistor won't count as part pf bulk-poly cap.

diffext  0	; diffusion extension for each transistor

; n-channel resistance
resistance n-channel dynamic-high	10.0	2.0	3847.0
resistance n-channel dynamic-low	10.0	2.0	1856.0
resistance n-channel static		10.0	2.0	2472.0

; p-channel resistance
resistance p-channel dynamic-high	20.0	2.0	2020.0
resistance p-channel dynamic-low	20.0	2.0	3969.0
resistance p-channel static		20.0	2.0	2011.0