#ifndef INSN_H #define INSN_H /* insn.h: Instruction encoding definition * $Id: insn.h,v 1.3 2003/06/06 21:31:15 martinus Exp $ */ /* This file is part of `exhaust', a memory array redcode simulator. * Copyright (C) 2002 M Joonas Pihlaja * Public Domain. */ /* * Instruction encoding: * * Instructions are held in a insn_t typed struct with three fields: * in: instruction flags, opcode, modifier, a-mode, b-mode * a: a-value * b: b-value * * The layout of the `in' field is as follows: * * bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * field | flags | |- op-code -| |-.mod-| |b-mode| |a-mode| * * Currently there is only one flag, the fl_START flag, which * the assembler uses to figure out the starting instruction * of a warrior (i.e. the one given by the START label). */ #define mBITS 3 /* number of bits for mode */ #define opBITS 5 /* bits for opcode */ #define moBITS 3 /* bits for modifier */ #define flBITS 2 /* bits for flags */ /* Positions of various fields */ #define maPOS 0 #define mbPOS (maPOS + mBITS) #define moPOS (mbPOS + mBITS) #define opPOS (moPOS + moBITS) #define flPOS (opPOS + opBITS) /* Various masks. These extract a field once it has been * shifted to the least significant bits of the word. */ #define moMASK ((1<>flPOS) & flMASK ) /* * OP(o,m,ma,mb): This macro encodes an instruction `in' field * from its various components (not flags). * * o: opcode * m: modifier * ma: a-mode * mb: b-mode * * e.g. OP(SPL, mF, DIRECT, BPREDEC ) * is a * spl.f $ , < */ #define _OP(o,m) ( ((o)<= AINDIRECT) // mode #define RAW_MODE(mode) ((mode) + (INDIRECT-AINDIRECT)) /* * flags */ enum { flB_START /* start label */ }; #define fl_START (1<= 0 \ ? (int)(x)%(int)(M) \ : (M) + ((int)(x)%(int)(M)) ) #define MOD(x,M) ( (x) % (M) ) #endif /* INSN_H */